library ieee;
use ieee.std_logic_1164.all;
entity mux81_system is
port(a,b : in std_logic;
sel : in sed_logic_vector(2 downto 0);
y : out std_logic);
end mux81_system;
architecture block1 of mux81_system is
component mux81
port(i1,i2,i3,i4,i5,i6,i7,i8 : in std_logic;
sel1 : in std_logic_vector(2 downto 0);
out_8 : out std_logic);
end component
signal or_sig,and_sig,xor_sig,nand_sig,nor_sig,nota_sig,notb_sig : std_logic;
