modelsim 시뮬레이션에서 자꾸 에러가 뜹니다.(verilog)

module nh400_top(
	clk,
	rst_x,
 
	// instruction memory
	imem_addr,
	idata,
 
	// data memory
	dmem_oeb,
	dmem_web,
	dmem_addr,
	dmem_rdata,
	dmem_wdata
 
);
 
input clk, rst_x;
input [15:0] idata;
input [3:0] dmem_rdata;
output [10:0] imem_addr;
output dmem_oeb, dmem_web;
output [3:0] dmem_wdata;
output [11:0] dmem_addr;
 
wire [11:0] pc_next, PC, pc_branch;
wire branch;
wire [15:0] inst;
wire [3:0] X, Y, ACC, SP;
wire [1:0] SR;
 
wire mem_read, mem_write;
 
wire write_x, write_y, write_acc;
 
wire write_sp, write_pc;
wire [1:0] write_sr;
wire [1:0] src_x, src_y, src_acc, src_sr, src_sp;
 
wire [3:0] wdata_x, wdata_y, wdata_acc, wdata_sp;
wire [1:0] wdata_sr;
 
wire [3:0] ex_oper1, ex_oper2;
wire [3:0] alu_op;
wire [3:0] ex_result;
wire [1:0] ex_flag;
wire [11:0] wdata_pc;
wire wait_mem, stall;
 
reg clear_pc;
 
always @(posedge clk or negedge rst_x)
begin
	if (!rst_x)
		clear_pc <= 1'b1;
	else
		clear_pc <= 1'b0;
end
 
assign wdata_pc = clear_pc ? 12'b0 : pc_next;
 
 
nh400_dec u_decoder(
	.clk (clk),
	.rst_x (rst_x),
	.inst (inst),
	.X (X), 
	.Y (Y), 
	.ACC (ACC),
	.SP (SP), 
	.PC (PC), 
	.SR (SR),
 
	// we need execution unit
	.ex_result (ex_result),	
	.ex_oper1 (ex_oper1),
	.ex_oper2 (ex_oper2),
 
	.mem_rdata (dmem_rdata),
	.mem_wdata (dmem_wdata),
	.mem_read (mem_read),
	.mem_write (mem_write),
	.mem_add (dmem_addr),
 
	.gpr_write ({write_acc, write_y, write_x}),
	.write_sr (write_sr),
	.write_sp (write_sp),	
	.write_pc (write_pc),	
	.src_x (src_x),
	.src_y (src_y),
	.src_acc (src_acc),
	.src_sr (src_sr),
	.src_sp (src_sp),
	.alu_op (alu_op),
 
	.wait_mem (wait_mem),
	.stall (stall),
	.branch (branch),
	.pc_branch	(pc_branch)
);
 
 
nh400_data_map u_data_map(
	// rename write_sr	
	.write_sr (write_sr),
 
	.src_x (src_x),
	.src_y (src_y),
	.src_acc (src_acc),
	.src_sr (src_sr),
	.src_sp (src_sp),
 
	.ex_result (ex_result),
	.ex_oper1 (ex_oper1),
	.mem_rdata (dmem_rdata),
	.ex_flag (ex_flag),
 
	.wdata_x (wdata_x),
	.wdata_y (wdata_y),
	.wdata_acc (wdata_acc),
	.wdata_sp (wdata_sp),
	.wdata_sr (wdata_sr)
);
 
nh400_spr u_spr(
	.clk (clk), 
	.reset (rst_x), 
	.SP (SP), 
	.SR (SR), 
	.PC (PC), 
 
	.write_sp (write_sp), 
	.write_sr (write_sr[0] || write_sr[1]), 
	.write_pc (write_pc), 
	.wdata_sp (wdata_sp), 
	.wdata_sr (wdata_sr), 
	.wdata_pc (wdata_pc)
);
 
nh400_gpr u_gpr(
	.clk (clk),
	.X (X), 
	.Y (Y), 
	.ACC (ACC), 
 
	.write_x (write_x), 
	.write_y (write_y), 
	.write_acc (write_acc), 
	.wdata_x (wdata_x), 
	.wdata_y (wdata_y), 
	.wdata_acc (wdata_acc)
);
 
nh400_dmemctrl u_dmemctrl(
	.clk (clk),
	.rst_x (rst_x),
	.mem_read (mem_read),
	.mem_write (mem_write),
 
	.dmem_oeb (dmem_oeb),
	.dmem_web (dmem_web),	
 
	.wait_mem (wait_mem)
);
 
 
// Project : you should replace these modules with your own modules (alu, fetch).
nh400_alu u_alu(
	.operation (alu_op), 
	.a (ex_oper1), 
	.b (ex_oper2), 
	.cin (SR[1]), 
	.zin (SR[0]), 
  .result (ex_result), 
  .cout (ex_flag[1]), 
  .zout (ex_flag[0])
);
nh400_fetch u_fetch(
  .clk (clk), 
  .rst_x (rst_x), 
  .stall (stall),
  .pc_next (pc_next), 
  .pc (PC), 
  .branch (branch), 
  .pc_branch (pc_branch), 	
  .imem_addr (imem_addr), 
  .idata (idata), 
  .instruction (inst)
);
 
 
 
endmodule