vhdl 초보인데요 질문드립니다.
안녕하세요.
10진카운터+fnd출력 + y출력4개인데요
카운트1일때y1출력하고 나머지는0
카운트2일때y2출력하고 나머지는0
카운트3일때y3출력하고 나머지는0
카운트4일때y4출력하고 나머지는0
y출력부분코딩이 오류가나는데
Error (10316): VHDL error at cntfndy.vhd(47): character ''1'' used but not declared for type "boolean"
Error (10327): VHDL error at cntfndy.vhd(47): can't determine definition of operator ""="" -- found 0 possible definitions
이거어떻게해결해야하나요?? 부탁드립니다
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cntfndy is
port(
nRst :in std_logic;
clk :in std_logic;
q :out std_logic_vector(3 downto 0);
fnd :out std_logic_vector(6 downto 0);
y1 :out std_logic;
y2 :out std_logic;
y3 :out std_logic;
y4 :out std_logic
);
end cntfndy;
architecture cntfndyarc of cntfndy is
signal sig_cnt : std_logic_vector(3 downto 0);
begin
process(nRst, clk)
begin
if(nRst = '0') then
sig_cnt <= (others => '0');
elsif clk'event and clk = '1' then
if (sig_cnt = 9) then
sig_cnt <= (others => '0');
else
sig_cnt<=sig_cnt + 1;
end if;
end if;
end process;
q <= sig_cnt;
fnd <= "1000000" when sig_cnt= 0 else
"1111001" when sig_cnt= 1 else
"0100100" when sig_cnt= 2 else
"0110000" when sig_cnt= 3 else
"0011001" when sig_cnt= 4 else
"0010010" when sig_cnt= 5 else
"0000010" when sig_cnt= 6 else
"1011000" when sig_cnt= 7 else
"0000000" when sig_cnt= 8 else
"0010000" when sig_cnt= 9 else
"1111111";
y1 <= sig_cnt = 0 when '1' else '0';
y2 <= sig_cnt = 1 when '1' else '0';
y3 <= sig_cnt = 2 when '1' else '0';
y4 <= sig_cnt = 3 when '1' else '0';
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